The LPC54102 MCU is an ARM Cortex-M4-based embedded application microcontroller. These devices include an optional ARM Cortex-M0+ coprocessor, 104 KB of on-chip SRAM, up to 512 KB of on-chip flash, five general-purpose timers, a state-configurable timer with PWM capability (SCTImer/PWM), and an RTC/ Alarm timer, a 24-bit multi-rate timer (MRT), a repeat interrupt timer (RIT), a windowed watchdog timer (WWDT), four USARTs, two SPIs, three high-speed slaves The mode of the ultra fast mode I 2 C bus interface and a 12-bit 5.0 MSPS ADC.
The ARM Cortex-M4 is a 32-bit core with many system enhancements such as low power, easy debugging, and high module integration. The ARM Cortex-M4 core CPU features a 3-stage pipeline and Harvard architecture with separate local instruction and data buses and a third bus for system peripherals, as well as an internal prefetch unit that supports indeterminate branch operations. The ARM Cortex-M4 supports single-cycle digital signal processors and SIMD instructions. A hardware floating-point unit is integrated in the kernel.
The ARM Cortex-M0+ coprocessor is an energy-efficient, easy-to-use 32-bit core that is compatible with the code and tools of the Cortex-M4 core. The Cortex-M0+ coprocessor delivers performance up to 100 MHz with a simple instruction set and reduced code size. In the LPC5410x, the Cortex-M0 coprocessor hardware multiplication is implemented as a 32-cycle iterative multiplier.
Lpc54102 pin configuration
On the LPC54102, digital pins can be grouped into two ports. Each digital pin may support up to four different digital functions, one analog function, including general purpose I/O (GPIO).
[1] PU = Input mode, pull-up resistor is enabled (pull-up resistor pulls the pin high to VDD). Z = high impedance, disable pull-up or pull-down resistors. The reset state reflects the state in which the pin has no startup code operation at reset. For the pin status in different power modes, refer to chapter 6.2.2 “Pin Status in Different Power Modesâ€. See Section 6.2.1 “Termination of Unused Pins†for terminations of unused pins.
[2] 5 V compatible pad with programmable interference filter (5 V tolerance in the presence of VDD; tolerance not exceeding 3.6 V in the absence of VDD); digital I/O with TTL level and hysteresis Function; standard drive strength. See Figure 27. The peak or interference pulse width of the input filter rejection is 3 ns to 16 ns (simulated value).
[3] True open drain pin. The I2C bus pins are compliant with the I2C bus specification and support I2C standard mode, I2C fast mode, and I2C ultra fast mode. This pin requires an external pullup to provide an output function. When the power is off, this pin is left floating and does not interfere with the I2C line. The open drain configuration applies to all functions on this pin.
[4] The 5 V-compatible pin provides standard digital I/O functionality with configurable modes, configurable hysteresis, and analog inputs. When configured as an analog input, the digital portion of the pin is disabled and the pin is not 5 V compatible.
[5] Reset pad. 5 V compatible pad with interference filter and hysteresis. The input filter rejects a spike or interference pulse width from 3 ns to 20 ns (simulated value).
[6] I = Input; AI = Analog Input; O = Output.
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