In various single-chip application systems, the normality of the chip memory is directly related to the normal operation of the system. In order to improve the reliability of the system, it is necessary to test the reliability of the system. Through testing, it can effectively find and solve the damage caused to the system due to memory failure. In this paper, several commonly used single-chip microcomputer RAM test methods are introduced in detail, and a RAM fault test method based on seed and bit-by-bit reversal is proposed.
First, RAM test method review
Method 1: A method of testing the system RAM is to check in two steps, and send #00H and #FFH to the entire data area successively, and then read and compare for comparison. If not, it indicates an error.
Method 2: Method 1 does not completely check the RAM error. In the reference, a standard algorithm MARCH-G for RAM detection is introduced. The MARCH-G algorithm provides excellent fault coverage, but the test time required is large. The MARCH-G algorithm needs to traverse the full address space three times. If the address line is "root", the CPU needs to access the RAM 6×2n times.
Method 3: A method of completing a test by shifting an address signal. On the basis that the address signal is all O, the signal of the address line Ai is inverted only once, while the signal of the other non-detected address line Aj(i≠j) is maintained at 0, so that the bit is shifted from the low bit to the high bit. Then, on the basis of the address signal being all ones, only the signal of the address line Ai is inverted once, while keeping the signals of other non-detected address lines Aj(i≠j) unchanged, also from the low position. The high position is carried out bit by bit. Therefore, the shift of the address signal is actually non-linearly addressed according to 2K (K is an integer, the maximum value is the width of the address bus), and the entire required address range can be regarded as being shifted by all 0s and all 1s. produced. Different pseudo-random data is written to the corresponding memory unit while the address changes. After the above write unit operation is completed, the address signal is shifted in reverse order to read the pseudo random data written and detected. If the address line is n, the CPU only accesses 2n+2 memory cells in the system RAM.
Second, based on seed and bit-by-bit reverse RAM test method
The seed-based and bit-by-bit reversal test method was further improved on the basis of method 3. The method 3 mainly uses the full O and all 1 background numbers to shift and expand. Compared with the MARCH-G algorithm, the fault coverage is slightly lower, but fewer address units are used. Here we refer to the number of backgrounds in Method 3 as "seeds". Take the RAM with 8 address lines as an example. The seeds take two numbers, 00000000 and 11111111, and take the numbers of 00000000, 11111111, 0000llll, and llll0000, and take 00000000, 11111111, 00001111, 11110000, 00110011, 1100llOO, 01010101, and 10101010. The eight-number shifting test is performed, and the fault coverage achieved is not the same. The improved method with the seed number of 2 is lower than the fault coverage of the MARCH-G algorithm. The improved method with the seed number of 4 is equivalent to the MARCH-G algorithm. The improved method with the seed number of 8 can exceed the effect of the MARCH-G algorithm. The improved method based on seed and bitwise inversion as a whole can replace the MARCH-G algorithm, but the number of addressing required for different seed numbers is also different. Set the address line to n, the number of seeds is 2, you need to access the RAM a total of 4" + 4 times, when the number of seeds is 4, you need to access the RAM a total of 8n + 8 times, when the number of seeds is 8, you need to access the RAM a total of 16n + 16 times, The MARCH-G algorithm needs to access the RAM for a total of 6×2n times. It can be seen that the improved method based on seed and bit-by-bit reversal has much lower test time overhead than the MARCH-G algorithm. At the same time, the fault coverage rate increases with the number of seeds. To improve, of course, the test time overhead required for different seed counts is different. In actual test applications, the appropriate number of seeds should be selected according to the test time and the test failure coverage rate to achieve satisfactory results.
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