In the LED data processing design, there are two ways to store data (Figure 1): 1 Packed Pixel Method: all bits of each pixel on the screen are stored in a single bank; 2 bit plane Bit Plane Method: Each bit of a pixel is stored in a different bank. Since multiple banks are used, they can read more pixel information at the same time. From the analysis of the two storage structures, the use of the bit plane structure is beneficial to improve the display effect of the LED screen.
Figure 1 Two ways of data storage
The block diagram of the entire LED display display control circuit is shown in Figure 2. The data reconstruction circuit completes the conversion of the RGB data, combines the same weights of different pixels, and then stores them in adjacent units, thereby completing the recombination of the entire data in the form of bits.
Figure 2 shows the control circuit
The data reconstruction circuit is mainly composed of four parts: an 8-bit data parallel transmission circuit; an 8-bit parallel-serial conversion circuit; an 8-bit data latch circuit; and an 8-bit plus 1 counter. Each 8-bit data of R/G/B is driven into the parallel latch by the pixel frequency of the synchronous processing, and the 8-bit plus 1 counter outputs the carry pulse LD, and the 8-bit data is simultaneously latched to the 8-bit parallel-serial conversion circuit. The clock control circuit completes the control of the parallel-to-serial conversion circuit clock. After the data is reconstructed, one bank is no longer a pixel value, but the same weight of different pixel values. All the same weights are stored together to form a bit plane storage structure in bits. The adjacent weights of each pixel must be taken out according to the opposite rule when reading.
Figure 3 data reconstruction circuit
The read and write address generator must meet strict timing. For the same memory chip, it can be divided into N slices (one pixel value is represented by N bits), each slice represents a bit plane, and when the pixel is converted to the same memory for writing, first write 0 bit, then write 1 bit. Finally, write N bits. For the 8Col×Row dot matrix display, there are 8Col×Row bits in each bit plane. The internal organization of the memory depends on the logical connection of the pixel tubes on the drive screen. According to the memory organization, the read address generator is driven by the column and then driven by the row; the write address generator uses the manner of driving the column and the column to drive the row, thereby ensuring read/write synchronization and correctly displaying the original image synchronously. letter.
Figure 4 Address Generator
Source: Weiku Electronics
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