Circuit function
The field effect transistor drain saturation current IDSS and pinch-off voltage VP are very different, so it is troublesome to determine the bias. Although there are several grades in the production plant, there are still differences in one grade. It is convenient to measure the VP and VOS in the actual working current state before assembling the circuit. When measuring, use the transfer switch to select the resistor R1~3, set the working current, and the R value can be calculated by R=15/ID.
Circuit working principle
In the OP amplifier inverting amplifying circuit, the current flowing through the feedback loop is made equal to the current determined by the input resistor, and thus the FET drain current EB is determined by the gate voltage VGS. That is, the OP amplifier A1 constitutes a servo circuit, and the potential of the inverting input terminal is controlled by the output of A1 so that the base is equal to zero.
Zener diodes D3 and D4 generate a voltage of ±9V to clamp the gate voltage of the object under test (DUT) so that the circuit does not apply an abnormal voltage. R5 is a current-limiting resistor that controls the gate current so that the base is not too large (usually almost no current flows).
FETs are available in both N-channel and P-channel versions, so SW1 can be used to switch the polarity of the input voltage to meet the needs of both models. When the test switch SW2 has no DUT, the gate terminal voltage is higher than the pinch-off voltage, the output of the OP amplifier is negative for NOA, positive for POH, and the output of the OP amplifier is VGS for normal test. When the operating current ID is 1 UA, R1=15/10-6th power=15M, IB=100UA, R2=15/10-4=150K, ID is 1MA, R3=15/10 third power =15K, R1~R3 ​​should be calculated according to the requirements of use.
Comment
Self-made circuit of FET
The figure shows a normal N-communication J-FET self-biasing circuit, which changes the set point Q due to the error of the pinch-off voltage VP or the drain saturation current IDSS.
If the voltage generated across the source resistor RS is used as the gate bias, set the Q point. After considering the influence of VP and IDSS, the RS can be calculated by the following equation.
The larger the RS, the more the error can be absorbed. However, due to the limitation of the operating current IDQ, it is necessary to select an appropriate resistance value or use a fixed bias circuit.
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