Abstract: The Virtex FPGA chip is one of the Xilinx chipset series. The data flow and configuration logic of the Virtex series are significantly different from those of the XC4000, but they are very compatible with the Xilinx FPGA family. . The data flow size and structure of the Virtex series FPGA chip are described in detail here.
1 IntroductionVirtex supports some new and very powerful configuration modes, including partial reconfiguration, which is designed into advanced applications to enable access to and operation of on-chip data through the chip's configuration interface. But to configure the chip, an understanding of its data flow structure is essential. An overview of the data flow structure of the Virtex family is presented here, describing the location of each bit in the data stream, which is important for accessing and changing on-chip data.
The data stream of the Virtex series can be regarded as the set of points determined by the address and data of the whole chip. The vertical direction is the address and the horizontal direction is the data. The set of points determined by the two-dimensional coordinates constitutes a whole block. The data flow of the chip. The address space of the whole chip is divided into two different block types, one is the CLB block type and the other is the RAM block type. Each type of address is divided into a number of frames and associated primary addresses, attached addresses, etc., which will be specifically described below.
2 frame, block type, primary address, attached address 2. 1 frameVirtex configuration memory can be displayed in an array of bits. This involves the concept of "frame", which is the basic unit of configuration. It consists of bits, width equal to one bit wide, and length equal to the top to bottom of the chip array. A frame is the smallest part that can be read or written from the configuration memory.
Frames are organized into larger units called columns. In Virtex, Virtex-E and Virtex-Eextended memory devices, there are different types of columns. As shown in Table 1.
Each Virtex device contains a central column with a global clock port configuration in the center column; two IOB columns, the IOB column describes the configuration of all IOBs on the left and right sides of the device; the most columns are CLB columns, and the CLB column contains The CLB of this column and the configuration of the IOB corresponding to the top and bottom of the CLB; the remaining two column types are RAM columns: one for the block RAM content column and the other for the block RAM interconnect column.
2. 2 block type, primary address, attached addressAll address spaces are divided into two block types: RAM block type and CLB block type. The RAM block type contains only the block SelectRAM content column (not including the interconnect). The CLB block type contains all other column types.
The RAM address and CLB address are further subdivided into a primary address and an attached address. Each configuration column has a unique primary address in the RAM or CLB address space, and each configuration frame has a unique attached address in its column.
Virtex, Virtex-E and Virtex-E extended memory devices have the same encoding order as the block type and attached address. The primary address encoding order is different for different series of devices. However, in both series, the even address is on the left half of the device, and the odd address is on the right half of the device. The CLB address space begins with a "0" in the middle column, then alternates between the right and left half of the device, then the IOB column, and finally the block SelectRAM interconnect column. The "0" of the RAM address space is the left block SelectRAM content column, and the "1" is the right block SelectRAM content column. As shown in Table 2, the frame position of XCV50 is assigned, and the last action is the primary address.
The size of the frame depends on the number of lines in the device. The number of configuration bits for a frame is equal to 18X ( # CLB_rows + 2) plus padding. For pipeline operations, the padding word is added to the end of each frame, with 0 as the padding, so that the number of configuration bits per frame is an integer multiple of 32. Table 3 shows the frame sizes of several Virtex devices. This table also shows the bitstream size of the CLB address space and the number of words per RAM block.
3. 2. 1 CLB frame structure In the device, each frame is in the vertical direction. Table 4 shows the structure of the CLB frame, and the front of the frame is the upper end (the order of the bits in the frame is from top to bottom). For the CLB column, the first 18 bits control the upper two IOBs, the next 18 bits allocate the CLB of each row; the last 18 bits control the bottom two IOBs, and the last frame adds enough padding bits "0" Make it an integer multiple of 32 bits.
3. 2. 2 IOB frame structure For each IOB frame on both sides of the chip, every three IOBs are allocated 18bits, and finally padding bit "0" is added to make it an integral multiple of 32. As shown in Table 5.
3. 2. 3 RAM frame structure For the block SelectRAM content frame, as shown in Table 6, the first 18bits is the PAD bit, then 72bits is allocated for each RAM line; the last 18bits is the PAD bit, and enough padding bits are added to the frame. It becomes an integer multiple of 32 bits.
Example XCV300 chip, array size is 32X48, in the generated. In the bin file, there are 51,975 32-bit words and 2475 CLB frames.
5 ConclusionIn the Virtex chip, the data stream is composed of frames. The size of the data stream depends on the array size of the chip. The last bit of each frame in the data stream is padded with a "0" to make it an integer multiple of the 32-bit word. The frames are connected in the order of the primary address, which forms the complete Virtex data stream. Understanding the frame structure and each bit in the frame is important for reading back the chip configuration or reconfiguring the data stream.
ShenZhen Haofa Metal Precision Parts Technology Co., Ltd. , https://www.haofametals.com